Program memory references are 32-bit logical addresses. The
4 high order bits of the logical address index a set of segment registers,
each of which contains a 24-bit ``virtual segment identifier''(VSID).
The logical address is
concatenated with the VSID to produce a virtual address.
There is a translation look-aside buffer of cached virtual 
physical
translations and hashed page tables indexed by a (hashed) virtual
address.
The tables are organized into ``buckets'', each consisting of
eight page table entries (PTEs). Each PTE contains a 20-bit physical page address,
a 24-bit virtual segment identifier (VSID) and permission and
other housekeeping information.
Once a TLB miss occurs, a hash function is computed on the virtual address
to obtain the index of a bucket. If no matching entry is found in this
bucket, a secondary hash function is computed to find the index of an
overflow bucket. If no entry is found in either bucket, the OS must
determine further action. On the 604, a TLB
miss causes the hardware to compute the hash function and search the
hash table. If no match is found, a page fault interrupt is generated
and a software handler is started. On the 603, there are registers
to assist hashing even though the hardware does not require software to
store PTEs in a hash table. Since a TLB miss is handled in hardware,
the 604 has a hash-table miss interrupt rather than a TLB miss interrupt.
The PowerPC also offers an alternative translation from logical to physical that bypasses the TLB/hash-table paging mechanism. When a logical address is referenced, the processor begins the page lookup and, in parallel, begins an operation called block address translation(BAT). Block address translation depends on eight BAT registers: four data and four instruction. The BAT registers associate virtual blocks of 128K or more with physical segments. If a translation via the BAT registers succeeds, the page table translation is abandoned.
