Transmeta system

Our Transmeta system contains a TM5400-633 Crusoe $^{\text {TM}}$ processor and 128 MB of memory (64 MB of SDRAM and 64 MB of DDRAM). 16 MB of this memory is reserved for the Code-Morphing Software, whose primary function is to dynamically translate x86 code to the underlying machine language of the VLIW chip. This code also implements LongRun $^{\text {TM}}$, the DVS policy Transmeta chips use. Transmeta told us how to override LongRun $^{\text {TM}}$ policies and change the speed ourselves.

The processor can run at 300-633 MHz and 1.2-1.6 V. Table 1 gives the available speeds and voltages, as well as the power the CPU consumes at each level. We measured power consumption by running a tight loop of additions while using hardware monitoring equipment Transmeta provided.

Table 1: Characteristics of the Transmeta processor at various settings

Speed	Voltage	Power	Energy/	Effi-
			cycle	ciency
297.3 MHz	1.2 V	1.349 W	4.537 nJ	0.5%
396.6 MHz	1.225 V	1.809 W	4.561 nJ	11.0%
497.8 MHz	1.35 V	2.714 W	5.461 nJ	11.8%
598.5 MHz	1.55 V	4.348 W	7.265 nJ	0.4%
631.1 MHz	1.6 V	4.915 W	7.787 nJ	N/A

We see that the 300 MHz and 600 MHz settings have very low efficiencies, and are therefore barely worthwhile. With only three reasonably worthwhile settings, we do not expect PACE to be very effective on this machine.

Incidentally, we note that the formula $1.179 \cdot 10^{-9} \cdot s^{3.41} + 3.681$, where $s$ is speed, gives a very close approximation to the energy consumption in nJ/cycle for all but the 300 MHz setting. The power of 3.41 differs substantially from the power 2 predicted by simple scaling models, e.g., in [21].