POWER4
The POWER4 [8] is a 64-bit microprocessor that contains two processors on each chip.
Four chips can be arranged on a module to form an 8-way machine, and
four modules can be combined to form a 32-way machine.
The POWER4 contains three cache levels as described in Table *.
There is one L1 data and one L1 instruction cache for each core on a chip.
The L1 caches are store through (write through); that is,
a write to the L1 is stored through to L2.
Two processors on a chip share an L2 cache.
The L2 cache is inclusive of the two L1 data caches, but not inclusive
of the two L1 instruction caches; that is,
any data in the L1 data cache also resides in the L2 cache. However,
data may reside in the L1 instruction cache that does not reside in the L2 cache.
The L2 cache is store in (write back); that is, a write to L2 is not written
to main memory (or L3).
Up to four L3 caches can be arranged on a module.
The L3 cache acts as a victim cache, storing cache lines that are
evicted from L2; therefore, the L3 cache is not inclusive of the L2 cache.
