Memory System Energy Model

For obtaining detailed profiles, we have customized an energy memory simulator and analyzer using the Shade [6] tool-set. Our memory simulator models on-chip instruction cache (Icache), on-chip data cache (Dcache), and off-chip memory, and allows the user to modulate the various parameters for these components. We characterize the overall energy of the memory system by the energy consumed by five components: the instruction cache, the data cache, the buses, the I/O pads and the main memory.

Note that we focus only on the dynamic energy consumption, since in current technology, the dynamic energy accounts for 80% of the total energy whereas the rest, short circuit and leakage, takes only 20% [14]. The energy consumed by the Icache and by the Dcache are evaluated using an analytical model that has been validated to be highly accurate, within 2.4% error, for conventional cache systems [16,25]. The energy consumed by the caches are based on technology related parameters for 0.8 micron technology. The energy consumption depends on the number of cache bit lines, word lines, and the number of accesses due to both hits and misses. The details of the model are quite involved and can be found in [22]. The address and data buses between the Icache/Dcache and the datapath account for the energy consumed by the on-chip buses. The bus energy consumption is evaluated by monitoring the switching activity on each of the bus lines using a capacitive load of 0.5pF per line [39]. The energy consumed by the I/O pads and the external buses to the main memory from the caches is evaluated similarly for a capacitive load of 20pF per line. The main memory energy is based on the model in [25] and uses a per main memory access energy, referred as E_m in the rest of the paper of $4.95\times$10^-9 Joules. A 32 megabyte main memory recommended as smallest memory size for running SPEC JVM98 benchmarks [27] is used in this work. The energy consumed by main memory accesses is further broken down into that consumed due to instruction accesses (Imemory) and data accesses (Dmemory).