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shows the percentage energy breakdown for the interpreter and the JIT modes assuming
32 KB two-way set associative instruction and data caches.
We see from the figure
on the left that most of the energy in the JIT mode is due to memory accesses for data (Dmemory).
In contrast, the memory energy due to native SPARC instruction accesses is lower.
This is because the instruction accesses exhibit much better data locality
and cause less number of off-chip accesses.
The same trend is also observed with the interpreter mode of operation
as shown in the graph on the right.
The instruction accesses
in the interpreter mode have better locality than the JIT mode [23],
and as a result, the percentage of the instruction
cache energy is higher in the former, especially for compress.
As an example, in the interpreter mode, instruction cache energy
consumption for the javac benchmark is
12.3% of the overall memory system energy, whereas the
corresponding figure in the JIT mode is 8.7%.
The energy consumption for a given unit
is directly related to the
number of accesses and per access energy cost [37].
It can be observed from Figure that the interpreter consumes significantly more energy than
in the JIT mode. A detailed breakdown of energy is shown in Figure .
This is due to the fact that both the number of instructions and number
of data accesses in the interpreter mode are higher than the JIT mode.
For example,
javac consumes 2.15 times more energy in the interpreter mode as compared to the JIT mode. Thus, the
use of JIT compilers will be more beneficial not only in terms of performance
(as is well-known [23]) but also from the energy viewpoint.
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