The PowerPC architecture uses a weak memory consistency model. The PowerPC instruction set includes two synchronization instructions: lwarx and stwcx. The first of these loads a word from an address memory while setting a reservation for the executing processor on this address (any reservation another processor may have on the address is cleared as a side effect). The second stores a word at an address provide the executing processor holds a reservation on the address. The success or failure of this operation is recorded in a condition register.
The IA32 architecture enforces stronger memory consistency among the multiple processors. The IA32 instruction set has a compare-and-swap instruction (cmpxchg): the value at a specified address is compared to a second value, if the two are equal, a third value is stored at the address. The success or failure of the operations can be obtained from a machine register. A locking prefix byte to this instruction makes its behavior appear atomic to any other processors.
The initial PowerPC implementation of Jikes RVM used methods of the VM_Magic class to directly emit lwarx and stwcx instructions. Rather than create architecture-specific classes for all the methods that called these methods, we designed VM_Magic methods that could be used on either architecture but whose implementations were architecture specific. We developed a synchronization idiom whereby attempting to perform a synchronized write first requires obtaining the old value using a prepare operation and then issuing an attempt operation which takes both the old and a new value as well as the raw address. Higher level pseudo-primitives, such as fetch-and-add, were implemented in Java using this discipline and provided as runtime utilities.
The int VM_Magic.prepare() method takes a raw address as its only parameter. On the IA32 architecture this is implemented as an ordinary load instruction. On the PowerPC it is a lwarx instruction.
The boolean VM_Magic.attempt() method takes a raw address and two (32 bit) values as parameters. On the IA32, it causes the corresponding atomic compare-and-swap to be executed. On the PowerPC, the second parameter is ignored, while the other two are used by a stwcx instruction.7In either case, the success of the operation is returned as the result of the method.