Prototype Design

Figure 4: Power consumption of the Actel Igloo AGL600V2 core having a simple 32-bit counter instantiated. We can clearly see the linear power behavior as expected from theory. Note that this FPGA is slightly bigger than the one used in our prototype, and thus consumes about 30$\mu W$ more static idle power.

The TI MSP430F1611 was a good fit for a first prototype. The MCU has two flexible timer units and the possibility to connect them to two individual crystals. Additionally, it has very low power consumption during sleep ($<10 \mu A$). However, for faster clocks, the 16-bit wide counters of the timer units are too small and overflow far too often. This leads to MCU wake-ups just to treat the overflows, increasing the average power consumption substantially. In addition, it inhibits the possibility of having other tasks running on the MCU directly, like sensing, control applications, or communication. For this reason, we based the next version of the STU on an FPGA. This allows us to implement the timer features we need and optimize the design for low power. We retained low power MCU for rapid prototyping and algorithm testing.

The FPGA needs to work at a very low-power active mode, have a small form factor, but at the same time be cheap in order to be viable for a large deployment. One such candidate is the Actel IGLOO Family[1] of FPGAs. They come in a variety of configurations, ranging from a 15k gate, 12 $\mu W$ static idle to a 1M gates, 59 $\mu W$ static idle power consumption, ARM-Enabled chip. For our prototype, we chose a mid-range sized FPGA, the AGL125V2, which is a good compromise between number of system gates (125k), to power consumption (20 $\mu W$ static idle). In addition, it can operate at 1.2V, which allows an even smaller power consumption during run-time (see Figure 4).

The only drawback of an FPGA is the longer turn-around time for prototyping compared to a MCU. Therefore, we decided to keep in addition to the FPGA a TI MSP430F1611 which can handle different parts of the algorithm, and provide a quick prototyping platform. Figure 5 depicts the interconnections between the FPGA and the TI MSP430. In addition to the two large chips, the STU needs three crystal oscillators, two high frequency, and one low frequency one. The problem with the TI MSP430, as with many MCUs with similar capabilities, is that it only provides two crystal inputs. Therefore, the FPGA will work as an intermediary that can dynamically provide the different clock signals to the MSP430, two at a time. In addition, the FPGA can implement timers and counters by itself, and thus eliminate the restrictions of the 16-bit timers found on the MSP430.

Figure 5: STU prototype board in the LCC-68 form factor. It contains 3 oscillators (two fast, one 32kHz), one TI MSP430F1611 MCU, and an Actel Igloo AGL125V2 Low Power FPGA. The board will have a size of 24x24mm.

The decision of the form factor chosen for the STU prototype was inspired by [4]. The industry-standard LCC-68 (68 pin leadless chip carrier) provides an easy transition from prototyping to production systems, because the modules can be socketed, hand-soldered, or machine-assembled, without loosing any space for a connector, since the side of the board would else be unused. The only drawback would be that the LCC-68 form factor can not be stacked, though that is a minor concern for the current prototype.